1. Field of the Invention
The invention generally relates to microprocessor circuitry, and more particularly, to the development of wait states during data transfers.
2. Description of the Related Art
With the advances in integrated circuit technology, particularly that related to microprocessors, there is a disparity between microprocessor circuits and many of the support circuits, including memory, used with the microprocessor. As microprocessor speeds increase to 20 and 25 MHz and above, the speeds of the memory devices and various peripheral devices that interact with the microprocessor must increase in a like manner. However, for memory devices and other devices to increase at this speed, their cost generally increases quite dramatically, particularly if a technology type must be changed, for instance, from dynamic random access memory (DRAM) to static random access memory (SRAM). Therefore, to save cost in many designs, wait states are inserted in access cycles. The number of wait states that are inserted depends upon the particular speed of the microprocessor and the response times of the particular device being accessed. Customarily, this wait state generation is developed based on the address decode used to enable the particular device, which then in turn triggers wait state generation circuitry related to that particular device. While this is quite satisfactory for a completed design, where the various speeds of the parts utilized in the circuits vary, such as during development of the particular system or on a batch-by-batch or lot-by-lot basis, this particular device related decode and wait state generation becomes quite difficult. The wait state generation circuitry must be redesigned for each particular embodiment. If this is a problem that develops during development of the particular system, then this delays development time while these ancillary circuits are redesigned to implement the single change of the microprocessor, for example.
Therefore, it is desirable to be able to simply and easily change the number of wait states for a particular device without requiring a hardware redesign to perform that function.